1. Field of the Invention
The invention relates to a method for producing a rewiring printed circuit board with the aid of an anisotropically conductive substrate wafer. In particular, the method relates to a method for producing a rewiring printed circuit board with a silicon substrate wafer having plated-through holes in a regular arrangement.
2. Description of the Related Art
The further processing of integrated circuits into a housing, and also the construction of stacked arrangements of integrated circuits require so called rewiring printed circuit boards which ensure that the external terminals of the housing or of the stacked arrangement are connected to the individual pads of the integrated circuits.
The previous methods for producing such rewiring printed circuit boards have in the meantime encountered technological limits, since the rewiring conductor tracks (conductive lines) are patterned using a printed circuit board technology whose resolution limit has been reached.
Furthermore, when the rewiring printed circuit board is connected to the integrated circuits, which are usually fabricated in a silicon substrate, thermal stresses occur during operation, since rewiring printed circuit board and integrated circuit often have different coefficients of thermal expansion. For this reason, rewiring printed circuit boards having plated-through holes are already being fabricated from silicon material, and in which case passage connections can be formed by the plated-through holes through uncovered regions lying opposite one another on the substrate surfaces.
One problem in the production of such rewiring printed circuit boards consists, however, in the fact that hitherto the conventional technologies for processing silicon substrates have had to be combined with technologies for the application of conductor tracks by electro-deposition in the production of such rewiring printed circuit boards.
The simultaneous processing of the front and rear sides of a substrate wafer as proposed, e.g., in the document U.S. Pat. No. 6,379,781 B1 likewise cannot be carried out in a suitable manner by methods of silicon technology. In particular, the processes of producing the masking layer for defining the positions for the plated-through holes of the substrate wafer and the methods for patterning and applying the conductor tracks adversely affect one another on account of process parameters such as, for example, temperature, pressure, materials used, so that, according to the order of the method steps, either one of the masking layers on one of the surfaces of the substrate wafer or the conductor tracks on one of the surfaces of the substrate wafer are impaired by a subsequent process.